Single error correcting system utilizing maximum length shift register sequences



Dec. 10, 1963 N M. ABRAMSON 3,114,130

SINGLE ERROR CORRECTING SYSTEM UTILIZING MAXIMUM LENGTH SHIFT REGISTER SEQUENCES Filed Dec. 22, 1959 5 Sheets-Sheet 1 T- *T f "1 1 1 I I ERROR GATE R I DETECTOR U BIT n l I RECEPTION I AATAA'T A 19 1 i A L ERROR 16 UNIT {DATA =51- UNIT DATA 1 1 T J SOURCE 1 A E 15 I \M-SEQUENCE ERROR N AOR A M-SEQUENCE l GE ERT CORRECTOR GENERATOR "T5 T T \55 1 SHIFT I REGISTER PULSE 1 T 49 GENERATOR I T PULSE I GENERATOR 56 l T L J ENCODER 11 FIG DECODER (12 P19 1 d I 35 AND 56 l 0 b J\ c15 1 p P4 17 O O l d I d I AND 28 AND 116 29 b 1 LI 1 'L L 13 T F4 i T INVENTOR.

NORMAN M. ABRAMSON BY g ATTORNEY Dec. 10, 1963 N. M. ABRAMSON ,130

SINGLE ERROR CORRECTING SYSTEM UTILIZING MAXIMUM LENGTH SHIFT REGISTER SEQUENCES Filed Dec. 22, 1959 5 Sheets-Sheet 2 D11D10D9 De D? De D5 D4 D3 D2 D1 P4 P3 P2 P4 D41 D10 D9 D8 D7 D6 D5 D4 D5 D2 D1 01010100110 101001010100110 DATA fl CLOCK SHIFT m H M3 PIPZM OUT PUT LINE Dec. 10, 1963 N. M. ABRAMSON 3,114,130

SINGLE ERROR CORRECTING SYSTEM UTILIZING MAXIMUM LENGTH SHIFT REGISTER SEQUENCES Filed Dec. 22, 1959 5 Sheets-Sheet 3 FIG. 4

Dec. 10, 1963 N. M. ABRAMSON SINGLE ERROR CORRECTING SYSTEM UTILIZING MAXIMUM LENGTH SHIFT REGISTER SEQUENCES 5 Sheets-Sheet 4 Filed Dec. 22, 1959 D11 [1100905 D1 D5 D5 D4 D3 D2 D 1 DATA OUT SHIFT REGISTER 2345678910110 DATA I N FIG. 5

N. M. ABRAMSON. RRECTI Dec. 10, 1963 3,114,130 MUM 5 Sheets-Sheet 5 Filed Dec. 22, 1959 DATA OUT Q SHIFT REGISTER 1254561891011 4 P 3 P 2 P DH F 3 F 2 F 1 F DATA SHIFT 0 COMPARE RCORRECT FIG. 6

United States Patent 3,114,130 SINGLE ERROR CGRRECTING SYSTEM UTILIZ- ING MAXIMUM LENGTH SHHT REGISTER SEQUENCES Norman M. Abramson, Woodside, Calif assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Dec. 22, 1959, er. No. 861,257 11 Claims. (Cl. 340-'146.1)

This invention relates in general to systems for detecting, locating and correcting errors in a binary code group consisting of parity bits and data bits, and in particular to a system for correcting single errors in a code group wherein the bit positions checked by each parity bit are determined in accordance with a systematic arrangement.

Various arrangements have been suggested in the prior art for checking coded information which has been translated between two points. These arrangements may be classified generally as either error detecting arrangements or error correcting arrangements. An example of an error detecting arrangement is the now well known parity check arrangement in which a parity bit position is added to the data bit positions of a binary code group. In this arrangement the binary value of the parity bit is chosen so that each code group has an even number of binary 1 bits. A similar known arrangement employs the same concept except that the value of the parity bit is chosen so as to provide an odd number of binary 1 bits in each code group. Such arrangements are, of course limited to the function of merely detecting the presence of an odd nurnber of errors. They cannot detect an even number of errors, and they cannot locate or correct any errors.

An example of an error correcting system known in the prior art is represented by the system disclosed by Hamming et al. in US. Reissue 23,601 (US. 2,552,629). The theory of the Hamming code for single error correction may be readily understood by an analysis of the so-called parity check table. A parity check table corresponding to Table 2 in the above-mentioned reissued patent is reproduced below as Table 1 for convenience.

TABLE 1 Code Group Position Locator Parity Bit Subword X X X In the example represented by the above table a code group of seven bit positions is assumed, D -D representing data bit positions, and k -k representing parity bit positions. This table is a convenient way to indicate that pariy bit k checks bit positions of the code group indicated by an X; that is, k, checks bit positions 1, 4, 5 and 7; parity bit k checks bit positions 2, 4, 6 and 7; and parity bit k checks bit positions 3, 5, 6 and 7.

When the code group is received some of the bits may be in ernor. At the receiver three more bits k '-k (comprising the locator subword) are computed. The parity check bit k will be equal to 0 if parity bit of the received code group satisfies its parity check, and equal to 1 if parity bit k of the received code group does not satisfy its parity check. Parity check bits k and k depend on k and k of the received code group in the same manner.

If the code group of seven bits is translated correctly, k 'k will all be 0 assuming an even parity check. However, if one bit of the translated code group is received in error the locator subword k k (referred to by Hamming as the parity subgroup) will not be all 0s and, hence, a single error is readily detected. The particular bit position in which the detected error is located is indicated by the condition of the locator subword k '-k The locator words and the respective bit positions which they indicate vare in error are tabulated below in Table 2 for convenience, and correspond to Table 4 in the above mentioned reissued patent.

The above table referred to as the locator subword table is based on the following reasoning and may be construed by reference to the parity check Table 1. To locate a particular bit position whose value has been received in error a reception parity check must be made over the same selected bit positions used in initially determining the value of each parity bit k k If a correct parity is received over the selected bit positions associated with each of the parity bits the locator subword k -k is all Os. If an error occurs in bit position 1, k is aifected and becomes a 1, while k and k are not atfected, since thhese parity bits do not check bit position 1. Hence, the locator subword for an error in bit position 1 is 100. Similarly, the locator subword for an error in bit position 2 is 010, and for an error in bit position 3, 001. An error in bit position 4 affects both k and k and hence the locator subword for an error in this bit position becomes 110. Similar reasoning may be employed to show that single errors in bit positions 5, 6 and 7 result in the locator subwords shown in Table 2. The obtaining of diiferent locator subwords for indicating the bit position where a single error occurs is the basic concept on which the Hamming error-correcting system is based.

As explained by Hamming the parity check table for a single error correcting systeni satisfies two conditions. The first is that each bit position of the code group must be in a locator subword. The second condition is that the locator subword k '-k for each bit position of the code group must be different.

In many circumstances it is desirable to transmit a code group which has a relatively large number of bit positions. The main reasons for having a large number of bit positions is that the efficiency of a data transfer operation is greatly increased. For example, in a seven bit code group the ratio of redundant data to useful data is 3-to-4, while in a code group having 127 bit positions the ratio becomes 7-to-120. In providing a system that will generate seven parity bits from 127 bit positions with each parity bit checking a particular group of bit positions in the 127 bit positions, a very complex arrangement for assigning particular bit positions to a group" 3 In order to simplify the assignment operation the prior art has suggested that another condition be added to the two conditions set forth in the Hamming reissued patent for construction of a systematic parity check table. This occurring sequence. Stated somewhat differently, single error correction systems known in the prior art cannot achieve the simplicity of circuitry obtained by systemiz-- ing the assignment of the bit positions to be checked and, at the same time, maintain the simple circuitry obtained other condition allows the basic concept of the Hamming parity check table to follow a systematic approach when under the condition where the assignment process is not it is extended to code groups having a relatively large systemized. 7 a number of bit positions. This third condition is illus- The present invention provides a single error correctrated in the parity check table below, and may be stated tion system which maintains the advantages of a systemas follows; a series of binary digits which form the 10 atic assignment of the bit positions to be checked by cator subword for any bit position of the code group deeach of the parity bits while still allowing the data bits fines the number of the bit position in the code group and the parity bits to be transmitted in their proper when it is considered as a conventional binary number. order. The concept underlying the system may best be TABLE 3 7 1 2 3 4 5 a 7 s 9 10 11 12 13 14 15 Parity Binary Bits Order 1 D2 Di D4 D5 D5 D7 DB D9 DH! D11 P4 5 P2 l X X 1 X X 2 X X X 4 X X X s It will be seen from the above table that a locator subword for any bit position in the code group is the understood by reference to the parity check Table 4 below.

TABLE 4 1 2 3 4 5 G 7 8 9 10 11 12 13 14 15 Parity Bits D D; D3 D4 D5 D6 D7 D3 D9 D10 u P1 P2 P3 4 X X X X X r X X X X X X X X X X X X X X X X X binary equivalent of that position. For example, the locator subword for bit position 5 is 1010, and the locatcr subword for bit position 13 is 1011, which (when read from left to right) are the binary equivalents of decimal 5 and 13, respectively. Following a systematic approach in the construction of the parity check table results in a simplification of the parity bit assignment process in that a conventional binary counter may be employed in the system for generating gating signals which allow a particular group of bit positions to be checked by the respective parity bits. In the example above it will be seen that parity bit P is assigned to check the group of positions consisting of D1, D3, D5, D7, D9, D11, P3 and P The output signal from the first stage of the conventional four stage binary counter would provide the necessary gating signals to allow the appropriate bit positions to be checked by parity hit F Similarly, the output signal of the second, third and fourth stages would provide the correct gating signals to allow the appropriate bit positions to be checked by parity bits P P and P respectively.

While systematizing the parity check table in the above described manner results in simplification of the parity bit assignment process, it creates the need for additional circuitry in that at least one of the particular parity bits also checks a bit position of the code group which contains another parity bit at a time when the condition of the parity bit to be checked is not final. For example, in the systemized parity check table above the group of parity bits checked by P include parity bit positions 13 and 15 of the code group which are reserved for parity bits P and P However, if the code group is to be transmitted in a serial by bit fashion, P cannot be transmitted in its proper sequence, since its final value cannot be determined until P is determined. It can be shown that systemizing the parity check table in accordance with the above described process prevents the transmis sion of the data bits and the parity bits in a natural The bit positions to be checked by parity bit P are determined in accordance with an m-sequence. The term m-sequence is known in the art and may be defined by the output signal of one stage of a maximal length binary shift register having R stages. An m-sequence is merely a series of 0s of 2 l binary digits arranged in a predetermined order. A true m-sequence satisfies the condition that:

where 2 -l is the number of binary digits in the sequence before it repeats itself and the symbol a is employed to designate the value of the first binary digit in the sequence; a the value of the second binary digit in the sequence; (n the value of the third binary digit in the sequence; etc. The above equation may also be expressed as:

from an R stage maximal length binary shift register is tabulated below:

Number of stages Ditterent m-seguences TABLE '5 The number of different msequences obtained from an R-stage Iii-sequence generator also corresponds to the number of different groups of coefficients C -C which are available for m-sequences From the above table it will be seen that two different m-sequences may be obtained from a 4-stage maximal length linear binary shift register. When C C correspond respectively to 1100, the following m-sequence is obta ned.

When C C is 1001 the other m-sequence is obtained.

With relation to the general Equation 1 for an msequence, the first sequence shown above is expressed specifically as a =a +a In nonmathematical language this specific equation expresses the fact that the value of the fifth binary digit (a .t,=the mod. 2 sum of the values of the first binary digit (a and second binary digit (a For example, the fifth digit in the m-sequence (l) is obtained by binary addition (mod. 2) of the first digit (1) and the second digit (0). The following digits of the m-sequence are obtained in the same manner until 2 1 (15) digits are obtained. The m-sequence then repeats itself.

The second m-sequence is obtained in a similar manner, but since the coefficients C C are different, 1001, the specific equation becomes a =a +a In other words the value of the first digit plus the value of the fourth digit will give the value of the fifth digit.

Referring again to the parity check table employed in connection with the present invention, it an X is replaced by a 1 and a blank by a 0 in each of the rows P -P of the table, it will be seen that the sequence of 0s and 1s follow the m-sequence defined in line 10, column 5, Where coeflicients C -C corresponds to 1001. The row designated P in the table corresponds exactly to the m-sequence in line 10, column 5. The succeeding rows are merely shifted one position to the right. The output signals of the first stage of a four-stage maximal length binary shift register would provide the necessary gating signals to allow the appropriate bit positions to be checked by P Similarly, the second, third and fourth stages of the shift register would provide the necessary gating signals to allow the appropriate bit positions to be checked by parity bits P P and P respectively.

The assignment of the bit positions to be checked by each parity bit follows a systematic approach, and hence the assignment operation is readily implemened in the error correcting system. In addition, since each of the parity bits are in a final state at the time they are to be transmitted, the parity bits may be transmitted sequentially following the data bits in a serial by bit fashion Without interruption.

In accordance with the present invention, the improved error correcting system comprises an encoder and a decoder which are interconnected by some suitable signal translating means. The encoder includes generally means to generate a predetermined number of parity bits depending upon the length of the code group to be transmitted, with each of the parity bits checking bit positions determined in accordance with an m-sequence, and means for transmitting the data bits and the parity bits to the decoder in the order in which they appear in the code group.

The decoder comprises generally means for making a reception parity check on bit positions of the code group which are determined in accordance with the m-sequence employed by the encoder, means operable in response to the generated reception parity bits for detecting an error, and means under the control of said generated reception parity bits for locating and correcting any single error which occurs in the code group.

It is therefore an object of the present invention to provide an improved system for correcting errors which occur during transmission of binary coded data.

Another object of the present invention is to provide an improved system for correcting single errors in a code group of transmitted data.

A further object of the present invention is to provide in an error correcting system which transmits a .code group consisting of sequential data bit positions followed by sequential parity bit positions, systematic means for assigning bit positions of the code group to be checked to parity bits in a manner to allow each ofthe parity bits to obtain a final condition by the time the parity bit position of the code group has been reached.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodi ment of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIG. -1 is a block diagram of the system;

FIG. 2 is a schematic view of the encoder embodying the invention;

FIG. 3 is a chart illustrating the operation of the encoder;

FIG. 3A is a parity check table similar to that shown in column 4 of the specification;

FIG. 4 is a schematic view of the decoder embodying the present invention;

FIG. 5 is a chart illustrating the operation of the decoder when no error occurs during transmission of the code group; and

FIG. 6 is a chart illustrating the operation of the decoder when a single error occurs during transmission of the code group.

Referring to the drawings, and particularly to FIG. 1, an error correcting system embodying the present inven tion is illustrated in block form in FIG. 1. The system includes an encoder 11 and a decoder 12 which are interconnected by some suitable signal translating means 13.

The data translating means 13 interconnecting the encoder 11 and decoder 12 may take several forms, depending on the particular application involved. For example, the translating means 13 may represent either a commercial telephone link or a radio telephone link connecting one of a plurality of remote input stations to a centrally located data processing center, in which event the'encoder :11 of the error correcting system is located in proximity with the remote input station and the decoder 12 is associated with the central data processing center. In another practical application, the data source and the utilization device may both be physically located in the same data processing unit, in which event the data translating means 13 interconnecting the encoder 11 and decoder 12 would employ in its simplest form a single conductor.

' In the latter application, certain, functional components common to both the encoder and the decoder could be eliminated in either the encoder or the decoder. However, since the first arrangement employing the encoder and the decoder at remote points lends itself to a more straight-forward explanation of the system, the invention is illustrated and described as embodied in this arrange ment. It is assumed that the system operates on a code group having fifteen positions consisting of eleven data bit positions and four parity bit positions, although any code group length greater than tWo may be employed, if desired.

As shown in FIG. 1, the encoder comprises an m-sequence generator 15, a gate unit 1 6, a parity bit register 17, a gate unit 19 and a generator of timed pulses 18. The details of the encoder may be seen by reference to FIG. 2.

The m-sequence generator 15, as shown in FIG. 2, is similar to a conventional four-stage shift register except that a feedback path is established through the exclusive OR circuit 21 from the output of the first and fourth stages F and F back to the first stage F The output of each stage P of the illustrated m-sequence generator provides the same m-sequences. However, the lit-sequences are shifted relative to each other by one position. The msequence may be seen in H6. 3 where the output of each stage F -F of the m-sequence generator 15 is tabulated. It will be noted that each of the columns F 43; define the same fifteen digit m-sequence. However, the lit-sequences in columns F F and F are shifted relative to the m-sequence in column F The particular m-sequence illustrated may be defined by the equation a +a =a 4 Generator 15 is started at a point in the sequence which allows stage F to provide a series of three Us at the end of the first cycle. Each stage of the m-sequence generator 15 is connected to the pulse generator 13 and is supplied with shift pulses Sal-S15. The output of the stages F F are connected to the gate unit 16.

Gate unit 16 comprises four conventional AND gates 2629 which are similar. Each AND gate has a pair of input terminals a and b and an output terminal 0'. Output terminal d is in a high state only when both input terminals a and b are high. The output signal of each stage F of the m-sequence generator 15 is supplied to terminal a of a different one of the AND gates 26-29.

The other terminal b of each AND gate is connected in parallel to an imput AND gate 30 which in practice may be incorporated in the data source and conditioned under the control of clock pulses Cit-C11 from pulse generator 18. The output tap d of AND gates 26 through 29 are connected to the parity bit register 17.

The parity bit register 17, as shown, comprises four stages P -P Any suitable bistable device known in the art may be employed for a stage of the register. For example, the bistable devices P P may be conventional Eccles-Jordan triggers arranged to change states alternately in response to successive pulses applied to input taps a. The output tap at of AND gate 26 is connected to the input tap a of stage P of register 17. The output taps d of AND gates 27, 28 and 29 are sirnilarly connected to input taps a of stages P P and P respectively. The output taps d of the stages P P are connected to the data-out line 13 through a gate unit 19.

In this instance the gate unit 19 comprises four conventional AND gates 33-36 which have their output taps d connected to the input of a four terminal OR circuit 37. Input taps a of AND gates 3336 are connected to the pulse generator 18, each tap being supplied with a separate clock pulse to condition the respective AND gates. The input taps b of AND gates 33-36 are supplied with signals from the four stages P P respectively, of register 17. The output terminal d of OR gate 37 is connected to the data-out line 13.

The operation of the encoder may be seen by reference to FIGS. 3 and 4. It is assumed that the m-sequence generator 15 and the parity bit register 1'7 are in the condition shown on line 1 of the chart and that the eleven bits of data D D are supplied from the data source in the order shown in the third column of the chart.

The first shift pulse S1 causes the m-sequence generator 15 to change from the 0001 start condition to the 1000 condition. In this condition stage F conditions AND gate 26 of unit 17 so that the data bit position D may be checked for parity by P The first data bit D is clocked out from the data source during clock pulse time Cl and is supplied to the data-out line 13 and the gate unit 16 simultaneously. It the first data bit contains a 1 output tap d of AND gate 26 will rise causing stage P to change state. In the present example D is 0 and, hence, P does not change state.

Shift pulse S2 thereafter causes the m-sequence generator to advance to the 1100 condition. Stages F and F therefore condition AND gates 26 and 27 allowing the next data bit D which in the present example is a 1, to pass through AND gates 26 and 27. Stages P and P olf1 register 17 therefore change states as indicated in the c art.

8 The above operation is continued until the data bit positions D -D have been checked for parity. Clock pulses C12Cll5 applied to AND gates 3336, respectively, of gate unit 1% cause the generated parity bits P P to be clocked out sequentially without interruption following the group of data bits D D Parity bits P P are also supplied to gate unit 16 so that bit position P of the code group may be checked by parity bit P Supplying parity bits 1 -1 to gate unit 16 also returns the parity bit register to its initial starting condition of 0000 so that the encoding of tie next code group may begin immediately, if desired. The eleven data bits D D and the four parity bits 1 -1 as shown on the last line of FIG. 3, are translated to the decoder 12 by the signal translating means 13.

Referring again to FIG. 1, the decoder, as shown therein, comprises a shift register 4-9, an m-sequence generator Sit, a gate unit 51, a reception parity bit register 52, an error detector 53, an error locator 54, an error corrector 5'5, and a pulse generator 56. The details of the encoder are shown in FIG. 4. As shown therein the shift register 49 comprises eleven stages l-ll. Data is supplied to the first stage from the signal translating means 13 through a pair of serially connected AND gates 60 and 61. AND gate 6% has one input tap a which is connected to the error detector unit 53 and is normally high, provided that an error has not occurred in the last code group which was received; a second input tap b which is connected to the signal translating means 13; and a third input tap c which is connected to the pulse generator 56 and is supplied with clock pulses (ll-C15.

The output tap at of AND gate 60 is connected to gate unit 51 and to input tap a of AND gate 61. The other other input tap b is connected to the pulse generator 56 and is supplied with clock pulses C1-C11. Output tap d of AND gate 61 is connected to the input of stage 1 of the shift register 49.

M-sequence generator 50, gate unit 51 and reception parity register 52 are identical to the m-sequence generator l5, gate unit 16, and parity bit register 17,'respectively, of the encoder 131, and hence the detailed description of these units is not repeated here. Generally, msequence generator 50 supplies four sampling signals to the AND gates 70-73 of gate unit 51, so that appropriate bit positions of the received code group are checked. The output tap c of AND gates 70-73 are connected to the stages RP -RP of the reception parity bit register 52.

The error detector 53 comprises a four terminal OR circuit Ethan inverter 81, a pair of AND gates 82 and 83, and an error trigger 84. The four input terminals a, b, c and d of OR circuit are connected to the respective output taps of stages Ri -RP, of register 52. Output terminal e of OR circuit 30 is connected to input tap a of error trigger 34 through inverter 81 and AND gate 82, and also to input tap b through AND gate 83. Taps b of AND gates 82 and 33 are connected to the pulse generator 56 and are supplied with an S1 pulse.

The error locator 54 is shown in block form in FIG. 4 and is connected to the output of stages RP RP of generator 52 and to the outputs of stages T -F of the lit-sequence generator 50. The error locator 54 functions to provide an output signal when the condition of register 52 corresponds to the condition of the m-sequence generator 5%. In this regard, the error locator unit may comprise any suitable signal comparing unit known in the art which provides an output signal in response to coincidence between a pair of four bit signals. For example, unit 54 may comprise four exclusive OR circuits which are connectcd to an inverter by a conventional OR circuit. Other arrangements are, of course, possible.

The error corrector unit 55 in this instance comprises a conventional AND gate 86 which has one input tap a connected to the normally low output tap c of the error trigger 64 and the other input tap b connected to the output of the error locator 54. Stage C associated with the shift register 49 may also be considered a portion of the error correcting means in that the condition of stage C is complemented in response to the output signal from tap c of AND gate 86 at the time the bit which is in error is present in stage C.

The operation of the decoder when no error occurs in translation of the code group may be seen by reference to FIG. which is a chart illustrating the decoding of the fifteen bit code group transmitted by the encoder 11. The chart of FIG. 5 is identical to the chart of FIG. 3, except that the first eleven bits are shifted into stages 111 of the register 49. Assuming error trigger 84 is set so that no-error tap d is high conditioning input AND gate 64), the fifteen bit code group is supplied to the AND gate 61 under control of the clock pulses C1-C15 from pulse generator 56. The eleven data bits are supplied to the shift register 49 through AND gate 61 under the control of clock pulses C1-C11,.and are shifted in from left to right under the control of shift pulses Sl-Sll applied to each of the stages of the shift register. M- sequence generator 50 provides the series of gating signals to condition gate unit 51 and allow reception parity checks to be made over the appropriate bit positions of the fifteen position code group. At the end of the reception parity check cycle each stage RP1-RP4 is O, and the output signal from OR circuit 60 is therefore low. AND gate 82 of the error detector is therefore conditioned by this signal being inverted while AND gate 83 is not conditioned. The first shift pulse S1 of the next cycle is therefore supplied to input tap a of error trigger 84, which has no effect on the condition of trigger 84. The cycle is then repeated for the next code group.

The operation of the decoder 12 in correcting an error which has occurred during translation from the encoder 11 may be seen by reference to FIG. 6, which assumes that the error has occurred in the eighth bit position of the code group, that is, data bit D is changed from a l to a 0.

FIG. 6 is a chart similar to FIG. 5, and since the operation of the decoder is identical to that which was just described up to the time that D; of the code group is supplied to gate unit 51, the chart begins at the time S7 has been supplied to gate unit 51. H-sequence generator 50 provides the same group of gating signals to gate unit 51 as in FIG. 5. However, since an error is present in the translated code group as received, the state of the reception parity bit register at the end of the cycle is not all Os. As shown in Chart 6, register 52 assumes a 1010 condition, and if the parity check table of FIG. 3A is consulted it will be seen that condition 1010 is the 10- cator subword for an error in the eighth bit position of the code group.

With 1010 in register 52, the output of OR circuit 80 is high conditioning AND gate 83, so that the S1 pulse of the next cycle applied to terminal b causes a signal to be supplied to terminal b of error trigger 84, resulting in a change of states. The normally high no-error tap d of trigger 84 therefore changes to a low state, while the normally low error tap 0 changes to a high state and conditions AND gate 86.

The input AND gate 60 is deconditioned by the drop of the no-error input tap d, and hence no data is supplied to either the shift register 49 or the gate unit 51 until the error is located and corrected. The reception parity bit register 52 therefore maintains its 1010 condition until the error is located. However, shift pulses S1415 supplied to the m-sequence generator 50 cause it to cycle while shift pulses S1-S11 supplied to the shift register 49 cause the group of data bits Dl-Dll stored in the shift register to be shifted out through stage C of the error correcting unit 55'. It will be seen from the lower portion of FIG. 6 that the condition of the m-sequence gen erator 50 and the reception parity bit register 52 coincide at shift pulse time S8. It should also be noted that at shift pulse time S8, the eighth position of the code group which contains the bit in error has been shifted into stage C of corrector unit 55.

Since AND gate 86 has been conditioned by the error signal from error trigger 84 at S1 time, the FRP com pare signal from the'error locator 54 at shift time S8 is supplied to stage C through AND gate 86 as a correctcommand signal. The correct-command signal causes the condition of stage C to reverse which, in effect, complements or corrects the value of the data bit presently in stage C. As shown in FIG. 6, the error in bit position 8 consisting of a 0 is corrected by changing it to a l. The corrected data bit D and subsequent bits D D are shifted out of the register through stage C to a suitable utilization device.

The reception parity bit register 52 in this instance is reset to the all 0 condition by the F-RP signal from the signal of OR gate 80. The signal supplied to terminal a of error trigger 84 causes the trigger to change states and restore the decoder to its original starting conditions The decoder will operate in the above described manner to correct automatically an error occurring in any of the data bit positions D D It will thus be seen that the present invention provides an error correcting systemin which the advantages of a systematic assignment process of the parity bits to be checked are obtained simultaneously with the advantages of transmitting the data bits and the parity bits in their normal sequence.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A system for correcting a single error in a binary code group consisting of a predetermined number of information bits and a predetermined number of parity bits, comprising: an encoder including a shift register, means responsive to the counts of said shift register and said information for identifying unique sets of bits in the code group and means responsive to said identifying means to generate the parity bits; signal translating means; and, a decoder coupled to said encoder through said signal translating means, said decoder including a shift register, means responsive to the counts of said shift register for identifying the sets in the received 'code group corresponding to those identified by said encoder identifying means, and means responsive to said identifying means and the bit values in the sets to generate a correction signal.

2. The combination recited in claim 1 in which the code group occurs serially by bit and said encoder identifying means assigns only code group bits to be checked by a parity bit which are prior to the parity bit in the code group.

3. A system for correcting single errors in a binary code group having K parity bit positions and 2 l or less total bit positions comprising in combination an encoder, signal translating means and a decoder connected to said encoder through said signal translating means and operable to correct a single error in any bit position in said code group caused during translation of said code group, said encoder comprising means for generating K parity bits including a register having K stages for storing said parity bits, a gate unit having K coincidence circuits, means connecting the output of each said coincidence circuit to the input of a different one of said regeach of said stages to correspond to an m-sequence, means connecting the output of each stage of said shift register to respective ones of said coincident circuits, means for advancing said shift register to cause K gating signals to be supplied to said gate unit, means for supplying data bits to said gate unit and said translating means after each advance of said shift register until (2 -1)K or less advances, and means for supplying one of said generated parity bits to said gate unit and said translating means after each of the last K advances of said shift register, saiddecoder comprising means for generating K reception parity bits over bit positions of said code group determined by said shift register of said encoder, and means responsive to the condition of said generated reception parity bits for detecting, locating and correcting a single error in any bit position of said code group.

4. The combination of claim 1 and means responsive to the correction signal of said decoder generator means to change the value of a bit of the received code group indicated by the correction signal value to have been incorrectly translated.

5. The combination of claim 1 wherein said shift registers operate cyclically through a maximum number of counts equal to the number of bits in the code group.

6. The combination of claim 5 wherein said shift registers include feedback connections between selected stages.

7. The combination of claim 6 wherein the feedback connections of said shift registers comprise exclusive OR circuits.

8. The combination of claim 1 wherein said encoder bit set identification means comprises a group of AND;

gates, each one responsive to one output of a different stage of said encoder shift register and'each one responsive to all of the information bits.

9. The combination of claim 8 wherein said encoder parity bit generator means comprises a set of stages, each one responsive to the output of a different one of said AND gates.

10. The combination of claim 1 wherein said encoder References Cited in the file of this patent UNITED STATES PATENTS 2,894,684 Nettleton July 14, 1959 OTHER REFERENCES Publication: J. H. Green, n, and R. L. San Soucie, An Error-Correcting Encoder and Decoder of High Efficiency, Proceedings of the I.R.E., October 1958.

Hagelbarger Oct. 11, 1960 

1. A SYSTEM FOR CORRECTING A SINGLE ERROR IN A BINARY CODE GROUP CONSISTING OF A PREDETERMINED NUMBER OF INFORMATION BITS AND A PREDETERMINED NUMBER OF PARITY BITS, COMPRISING: AN ENCODER INCLUDING A SHIFT REGISTER, MEANS RESPONSIVE TO THE COUNTS OF SAID SHIFT REGISTER AND SAID INFORMATION FOR IDENTIFYING UNIQUE SETS OF BITS IN THE CODE GROUP AND MEANS RESPONSIVE TO SAID IDENTIFYING MEANS TO GENERATE THE PARITY BITS; SIGNAL TRANSLATING MEANS; AND, A DECODER COUPLED TO SAID ENCODER THROUGH SAID SIGNAL TRANSLATING MEANS, SAID DECODER INCLUDING A 